24 ExportClustering() =
default;
25 void apply(ScheduleDAGInstrs *DAG)
override;
28static bool isExport(
const SUnit &SU) {
34 unsigned Imm =
TII->getNamedOperand(*
MI, AMDGPU::OpName::tgt)->getImm();
40 if (!PosCount || PosCount == Chain.
size())
49 unsigned OtherIdx = PosCount;
50 for (
SUnit *SU : Copy) {
51 if (isPositionExport(
TII, SU))
54 Chain[OtherIdx++] = SU;
62 for (
unsigned Idx = 0, End = Exports.
size() - 1; Idx < End; ++Idx) {
63 SUnit *SUa = Exports[Idx];
64 SUnit *SUb = Exports[Idx + 1];
69 SUnit *PredSU = Pred.getSUnit();
70 if (!isExport(*PredSU) && !Pred.isWeak())
85 SUnit *PredSU = Pred.getSUnit();
86 if (Pred.isBarrier() && isExport(*PredSU)) {
93 for (
const SDep &ExportPred : PredSU->
Preds) {
95 if (ExportPred.
isBarrier() && !isExport(*ExportPredSU))
103 for (
SDep Pred : ToAdd)
108 const SIInstrInfo *
TII =
static_cast<const SIInstrInfo *
>(DAG->
TII);
116 unsigned PosCount = 0;
117 for (SUnit &SU : DAG->
SUnits) {
122 if (isPositionExport(
TII, &SU))
125 removeExportDependencies(DAG, SU);
128 for (SDep Succ : Succs)
129 removeExportDependencies(DAG, *Succ.getSUnit());
133 if (Chain.
size() > 1) {
134 sortChain(
TII, Chain, PosCount);
135 buildCluster(Chain, DAG);
141std::unique_ptr<ScheduleDAGMutation>
143 return std::make_unique<ExportClustering>();
ReachingDefAnalysis InstSet & ToRemove
const HexagonInstrInfo * TII
Interface definition for SIInstrInfo.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
const T & front() const
front - Get the first element.
size_t size() const
size - Get the array size.
Representation of each machine instruction.
@ Cluster
Weak DAG edge linking a chain of clustered instrs.
@ Barrier
An unknown scheduling barrier.
@ Artificial
Arbitrary strong DAG edge (no real dependence).
bool isBarrier() const
Tests if this is an Order dependence that is marked as a barrier.
static bool isEXP(const MachineInstr &MI)
Scheduling unit. This is a node in the scheduling DAG.
LLVM_ABI void removePred(const SDep &D)
Removes the specified edge as a pred of the current node if it exists.
SmallVector< SDep, 4 > Succs
All sunit successors.
SmallVector< SDep, 4 > Preds
All sunit predecessors.
MachineInstr * getInstr() const
Returns the representative MachineInstr for this SUnit.
A ScheduleDAG for scheduling lists of MachineInstr.
bool addEdge(SUnit *SuccSU, const SDep &PredDep)
Add a DAG edge to the given SU with the given predecessor dependence data.
Mutate the DAG as a postpass after normal DAG building.
const TargetInstrInfo * TII
Target instruction information.
std::vector< SUnit > SUnits
The scheduling units.
void push_back(const T &Elt)
This is a 'vector' (really, a variable-sized array), optimized for the case when the array is small.
void apply(Opt *O, const Mod &M, const Mods &... Ms)
This is an optimization pass for GlobalISel generic memory operations.
class LLVM_GSL_OWNER SmallVector
Forward declaration of SmallVector so that calculateSmallVectorDefaultInlinedElements can reference s...
std::unique_ptr< ScheduleDAGMutation > createAMDGPUExportClusteringDAGMutation()