35#define DEBUG_TYPE "regalloc"
41 unsigned NumBlocks = MF->getNumBlockIDs();
43 Seen.resize(NumBlocks);
45 Map.resize(NumBlocks);
61void LiveRangeCalc::updateFromLiveIns() {
63 for (
const LiveInBlock &
I : LiveIn) {
67 assert(
I.Value &&
"No live-in value found");
78 Map[
MBB] = LiveOutPair(
I.Value,
nullptr);
81 Updater.
add(Start, End,
I.Value);
88 assert(
Use.isValid() &&
"Invalid SlotIndex");
89 assert(Indexes &&
"Missing SlotIndexes");
90 assert(DomTree &&
"Missing dominator tree");
93 assert(UseMBB &&
"No MBB at Use");
97 if (EP.first !=
nullptr || EP.second)
104 if (findReachingDefs(LR, *UseMBB,
Use, PhysReg, Undefs))
115 assert(Indexes &&
"Missing SlotIndexes");
116 assert(DomTree &&
"Missing dominator tree");
124 unsigned BN =
MBB.getNumber();
127 if (UndefOnEntry[BN])
132 DefOnEntry[S->getNumber()] =
true;
133 DefOnEntry[BN] =
true;
141 WorkList.
insert(
P->getNumber());
143 for (
unsigned i = 0; i != WorkList.
size(); ++i) {
145 unsigned N = WorkList[i];
148 const LiveOutPair &LOB = Map[&
B];
149 if (LOB.first !=
nullptr && LOB.first != &
UndefVNI)
150 return MarkDefined(
B);
152 SlotIndex Begin, End;
153 std::tie(Begin, End) = Indexes->getMBBRange(&
B);
159 if (UB != LR.
begin()) {
160 LiveRange::Segment &Seg = *std::prev(UB);
161 if (Seg.
end > Begin) {
168 return MarkDefined(
B);
174 if (UndefOnEntry[
N] || LR.
isUndefIn(Undefs, Begin, End)) {
175 UndefOnEntry[
N] =
true;
179 return MarkDefined(
B);
182 for (MachineBasicBlock *
P :
B.predecessors())
183 WorkList.
insert(
P->getNumber());
186 UndefOnEntry[BN] =
true;
196 SmallVector<unsigned, 16> WorkList(1, UseMBBNum);
199 bool UniqueVNI =
true;
200 VNInfo *TheVNI =
nullptr;
202 bool FoundUndef =
false;
205 for (
unsigned i = 0; i != WorkList.
size(); ++i) {
206 MachineBasicBlock *
MBB = MF->getBlockNumbered(WorkList[i]);
211 errs() <<
"Use of " <<
printReg(PhysReg, MRI->getTargetRegisterInfo())
212 <<
" does not have a corresponding definition on every path:\n";
213 const MachineInstr *
MI = Indexes->getInstructionFromIndex(Use);
220 const TargetRegisterInfo *
TRI = MRI->getTargetRegisterInfo();
222 for (MCRegAliasIterator Alias(PhysReg,
TRI,
false); !IsLiveIn && Alias.isValid(); ++Alias)
228 <<
", but is missing from the live-in list.\n";
237 if (Seen.test(Pred->getNumber())) {
238 if (VNInfo *VNI = Map[Pred].first) {
239 if (TheVNI && TheVNI != VNI)
246 SlotIndex
Start, End;
247 std::tie(Start, End) = Indexes->getMBBRange(Pred);
252 VNInfo *VNI = EP.first;
253 FoundUndef |= EP.second;
256 if (TheVNI && TheVNI != VNI)
260 if (VNI || EP.second)
265 WorkList.push_back(Pred->getNumber());
273 FoundUndef |= (TheVNI ==
nullptr || TheVNI == &
UndefVNI);
274 if (!Undefs.
empty() && FoundUndef)
279 if (WorkList.
size() > 4)
285 LiveRangeUpdater Updater(&LR);
286 for (
unsigned BN : WorkList) {
287 SlotIndex
Start, End;
288 std::tie(Start, End) = Indexes->getMBBRange(BN);
290 if (BN == UseMBBNum &&
Use.isValid())
293 Map[MF->getBlockNumbered(BN)] = LiveOutPair(TheVNI,
nullptr);
294 Updater.
add(Start, End, TheVNI);
300 EntryInfoMap::iterator
Entry;
302 std::tie(Entry, DidInsert) = EntryInfos.insert(
303 std::make_pair(&LR, std::make_pair(BitVector(), BitVector())));
306 unsigned N = MF->getNumBlockIDs();
307 Entry->second.first.resize(
N);
308 Entry->second.second.resize(
N);
310 BitVector &DefOnEntry =
Entry->second.first;
311 BitVector &UndefOnEntry =
Entry->second.second;
315 LiveIn.reserve(WorkList.size());
316 for (
unsigned BN : WorkList) {
317 MachineBasicBlock *
MBB = MF->getBlockNumbered(BN);
318 if (!Undefs.
empty() &&
319 !isDefOnEntry(LR, Undefs, *
MBB, DefOnEntry, UndefOnEntry))
323 LiveIn.back().Kill =
Use;
331void LiveRangeCalc::updateSSA() {
332 assert(Indexes &&
"Missing SlotIndexes");
333 assert(DomTree &&
"Missing dominator tree");
341 for (LiveInBlock &
I : LiveIn) {
346 MachineBasicBlock *
MBB =
Node->getBlock();
348 LiveOutPair IDomValue;
361 if (IDomValue.first && IDomValue.first != &
UndefVNI &&
363 Map[IDom->
getBlock()].second = IDomValue.second =
364 DomTree->getNode(Indexes->getMBBFromIndex(IDomValue.first->def));
368 LiveOutPair &
Value = Map[Pred];
369 if (!
Value.first ||
Value.first == IDomValue.first)
379 DomTree->getNode(Indexes->getMBBFromIndex(
Value.first->def));
384 if (DomTree->dominates(IDom,
Value.second)) {
394 LiveOutPair &LOP = Map[
MBB];
399 assert(Alloc &&
"Need VNInfo allocator to create PHI-defs");
400 SlotIndex
Start, End;
401 std::tie(Start, End) = Indexes->getMBBRange(
MBB);
409 if (
I.Kill.isValid()) {
411 LR.
addSegment(LiveInterval::Segment(Start,
I.Kill, VNI));
414 LR.
addSegment(LiveInterval::Segment(Start, End, VNI));
415 LOP = LiveOutPair(VNI, Node);
417 }
else if (IDomValue.first && IDomValue.first != &
UndefVNI) {
419 I.Value = IDomValue.first;
422 if (
I.Kill.isValid())
427 if (LOP.first == IDomValue.first)
440 BitVector DefBlocks(MF.getNumBlockIDs());
442 DefBlocks.
set(Indexes.getMBBFromIndex(
I)->getNumber());
444 unsigned EntryNum = MF.front().getNumber();
447 for (
unsigned i = 0; i != PredQueue.
size(); ++i) {
448 unsigned BN = PredQueue[i];
451 if (BN == EntryNum) {
458 PredQueue.
insert(
P->getNumber());
assert(UImm &&(UImm !=~static_cast< T >(0)) &&"Invalid immediate!")
This file implements the BitVector class.
static GCRegistry::Add< OcamlGC > B("ocaml", "ocaml 3.10-compatible GC")
static VNInfo UndefVNI(0xbad, SlotIndex())
static VNInfo UndefVNI(0xbad, SlotIndex())
Register const TargetRegisterInfo * TRI
SI Optimize VGPR LiveRange
This file implements a set that has insertion order iteration characteristics.
This file defines the SmallVector class.
ArrayRef - Represent a constant reference to an array (0 or more elements consecutively in memory),...
bool empty() const
empty - Check if the array is empty.
bool test(unsigned Idx) const
LLVM_ABI static LLVM_ATTRIBUTE_UNUSED bool isJointlyDominated(const MachineBasicBlock *MBB, ArrayRef< SlotIndex > Defs, const SlotIndexes &Indexes)
A diagnostic function to check if the end of the block MBB is jointly dominated by the blocks corresp...
void addLiveInBlock(LiveRange &LR, MachineDomTreeNode *DomNode, SlotIndex Kill=SlotIndex())
addLiveInBlock - Add a block with an unknown live-in value.
LLVM_ABI void resetLiveOutMap()
Reset Map and Seen fields.
LLVM_ABI void reset(const MachineFunction *mf, SlotIndexes *SI, MachineDominatorTree *MDT, VNInfo::Allocator *VNIA)
reset - Prepare caches for a new set of non-overlapping live ranges.
LLVM_ABI void extend(LiveRange &LR, SlotIndex Use, Register PhysReg, ArrayRef< SlotIndex > Undefs)
Extend the live range of LR to reach Use.
LLVM_ABI void calculateValues()
calculateValues - Calculate the value that will be live-in to each block added with addLiveInBlock.
void setLiveOutValue(MachineBasicBlock *MBB, VNInfo *VNI)
setLiveOutValue - Indicate that VNI is live out from MBB.
Helper class for performant LiveRange bulk updates.
void setDest(LiveRange *lr)
Select a different destination live range.
LLVM_ABI void add(LiveRange::Segment)
Add a segment to LR and coalesce when possible, just like LR.addSegment().
This class represents the liveness of a register, stack slot, etc.
LLVM_ABI iterator addSegment(Segment S)
Add the specified Segment to this range, merging segments as appropriate.
Segments::iterator iterator
LLVM_ABI std::pair< VNInfo *, bool > extendInBlock(ArrayRef< SlotIndex > Undefs, SlotIndex StartIdx, SlotIndex Kill)
Attempt to extend a value defined after StartIdx to include Use.
bool isUndefIn(ArrayRef< SlotIndex > Undefs, SlotIndex Begin, SlotIndex End) const
Returns true if there is an explicit "undef" between Begin End.
VNInfo * getNextValue(SlotIndex Def, VNInfo::Allocator &VNInfoAllocator)
getNextValue - Create a new value number and return it.
int getNumber() const
MachineBasicBlocks are uniquely numbered at the function level, unless they're not in a MachineFuncti...
const MachineFunction * getParent() const
Return the MachineFunction containing this basic block.
iterator_range< pred_iterator > predecessors()
LLVM_ABI bool isLiveIn(MCRegister Reg, LaneBitmask LaneMask=LaneBitmask::getAll()) const
Return true if the specified register is in the live in set.
DominatorTree Class - Concrete subclass of DominatorTreeBase that is used to compute a normal dominat...
MachineRegisterInfo & getRegInfo()
getRegInfo - Return information about the registers currently in use.
MachineBasicBlock * getBlockNumbered(unsigned N) const
getBlockNumbered - MachineBasicBlocks are automatically numbered when they are inserted into the mach...
bool verify(Pass *p=nullptr, const char *Banner=nullptr, raw_ostream *OS=nullptr, bool AbortOnError=true) const
Run the current MachineFunction through the machine code verifier, useful for debugger use.
Wrapper class representing virtual and physical registers.
constexpr bool isPhysical() const
Return true if the specified register number is in the physical register namespace.
A vector that has set insertion semantics.
size_type size() const
Determine the number of elements in the SetVector.
iterator end()
Get an iterator to the end of the SetVector.
iterator begin()
Get an iterator to the beginning of the SetVector.
bool insert(const value_type &X)
Insert a new element into the SetVector.
SlotIndex - An opaque wrapper around machine indexes.
SlotIndex getPrevSlot() const
Returns the previous slot in the index list.
const std::pair< SlotIndex, SlotIndex > & getMBBRange(unsigned Num) const
Return the (start,end) range of the given basic block number.
A Use represents the edge between a Value definition and its users.
VNInfo - Value Number Information.
BumpPtrAllocator Allocator
NodeAddr< UseNode * > Use
NodeAddr< NodeBase * > Node
This is an optimization pass for GlobalISel generic memory operations.
FunctionAddr VTableAddr Value
auto upper_bound(R &&Range, T &&Value)
Provide wrappers to std::upper_bound which take ranges instead of having to pass begin/end explicitly...
LLVM_ABI void report_fatal_error(Error Err, bool gen_crash_diag=true)
DomTreeNodeBase< MachineBasicBlock > MachineDomTreeNode
LLVM_ABI raw_fd_ostream & errs()
This returns a reference to a raw_ostream for standard error.
void array_pod_sort(IteratorTy Start, IteratorTy End)
array_pod_sort - This sorts an array with the specified start and end extent.
LLVM_ABI Printable printReg(Register Reg, const TargetRegisterInfo *TRI=nullptr, unsigned SubIdx=0, const MachineRegisterInfo *MRI=nullptr)
Prints virtual and physical registers with or without a TRI instance.
LLVM_ABI Printable printMBBReference(const MachineBasicBlock &MBB)
Prints a machine basic block reference.