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Technology and processing advances in semiconductors don't only benefit the glamour products, such as high-density memories and minicomputers on a chip. Rather, these improvements also gradually trickle down to the bread-and-butter devicesโonly without much fanfare. Case in point: uncommitted logic.
Unable to compete because of large die size and insufficient complexity, semicustom devices have until recently been obscured in the ยตP's shadow. And fuse-programmed logic has suffered much the same fate. But both logic types are now experiencing a revival of interest, based on improved architectures and logic density.
Several developments herald this revival:
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- The venerable field-programmable logic array (FPLA) now has some younger and smarter brothers. At the top of the line stands the field-programmable logic sequencer (FPLS)โbasically an FPLA redesigned as a state machine by the addition of a 6-bit state register with feedback to the inputs, along with an 8-bit output registerโboth tied to a clock line. Also available is the field-programmable ROM patch (FPRP), which can disable a ROM upon selection of an address with faulty information and substitute the correct information stored in its own summing matrix. Other members of this group are the field-programmable gate array (FPGA), which has a programmable product matrix but no summing matrix and serves for random-logic replacement, and the PMUX, a programmable multiplexer. (See box, โA review of field-programmable logic.โ)
- A class of programmable logic termed PALs (programmable array logic) has also appeared. Smaller and faster than FPLAs, these Monolithic Memories Inc devices incorporate a fixed summing matrix with a programmable product matrix. The 15-member family includes parts with registers and feedback provisions and has just picked up a major second sourceโNational Semiconductor. (See box, โA PAL review.โ)
- Semicustom arrays now have vastly improved density and functionalityโarray sizes stand in excess of 3000 gates, and the 5000-gate level is easily within reach and now under development. Manufacturers produce these semicustom ICs in virtually every silicon technology, allowing customers to optimize their products by employing a particular logic family or process. (See box, โThe semicustom concept.โ)
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But who gets the socket?
The advances in all of these product areas often seem to place semicustom and fuse-programmable logic in competition, at least at the lower levels of integration. However, opinions of manufacturers on both sides vary widely concerning the degree of this competition.
On the whole, though, the semicustom-IC people hardly see any overlap. Typical of their comments are those of Frank Deverse, president of International Microcircuits, who views fuse-programmable logic's current level of complexity and configurability as suiting it primarily for low gate densities. On the other hand, he sees semicustom arrays covering the entire range of densities and technologies, including linear. Deverse does note, however, that fuse logic enjoys an advantage with respect to development time and that the economics of semicustom devices are fully realized only at higher levels of gate utilization and volume.
Robert Lipp, president of California Devices, agrees and adds that semicustom logic can directly replace all of a system's random logic without requiring a redesign. He also points out other features of semicustom arrays that fuse logic can't provideโnot all on a single chip, anyway: interface capability among virtually any logic families, logic levels or power-supply levels; pull-ups; pull-downs; 3-state I/O; Schmitt triggers; oscillators; comparators; detectors; debounce control; and voltage regulation.
Dr Charles Allen, president of Master Logic Corp, emphasizes the security aspect of semicustom arrays when employed in propriety products. Programmable devices can find use in such individualized systems as electronic keys or serialized products, but Allen maintains that the ease with which persons can copy fuse-programmed parts effectively takes them out of the propriety-product business. Semicustom arrays, on the other hand, are as difficult to copy as stand ICs.
Motorola's Bill Blood stresses fuse-programmable products' rigidity of patterns and logic functions. How, for example, do you configure an LSI circuit that requires a 10-bit shift register if your field-programmable logic only contains eight flip flops? Similarly, you can't build an LSI part incorporating multiphase clocking on an array that connects all flip flops to a common clock line. Blood, manager of bipolar-LSI system engineering at the firm, does admit that creating a custom metal mask is a more complex operation than programming fuses at a user's site. But he stresses that manufacturers of semicustom arrays are addressing this problem with sophisticated CAD interfaces to cut development time and complexity.
Pick your technology
The upshot of all this is that if you decide the semicustom route is for you, you can choose among a variety of vendor capabilities. Table 1 outlines the technologies employed by each firm in the semicustom-IC business, and Table 2 elaborates on the basic characteristics of some firms' product offerings. Once you've determined the companies that produce ICs in the technology you need, you can use the following information, presented alphabetically by company name, to better understand each firm's package of design and development assistance spanning the product-development cycle. On the other hand, if you decide that the fuse-programmed approach better suits your needs, refer to Table 3 and Table 4 and the previously referenced boxes for additional data.
California Devices will take a design at any stage of development, from basic specification onward, and deliver working semicustom parts. Layout costs, including interconnect routing, digitization of the pattern and computer verification of design rules, runs from $600 to $6000 or more, depending on chip complexity. From mask generation through final test, prices start at $2400 (CDI50, CDI100) and range to $4800 (CDI800).
Development time from logic drawing to prototype delivery ranges from 5 to 10 wks, again depending on complexity and customer involvement. Currently, CDI's metal-gate CMOS family comprises eight devices, and the company is also introducing a high-speed silicon-gate CMOS line with chip complexities ranging from 300 to 1200 gates.
The CS-2000 and CS-3000 constitute Cherry Semiconductor's Genesis Linear Master Circuits; these 20V bipolar transistor/resistor arrays contain 187 and 437 components, respectively. The CS-3000 is a functional equivalent of the Exar XR-F100 and Interdesign Monochip MOF.
In specifying these products, you model a design in a discrete-component or transistor-array breadboard, then sketch the interconnect pattern for digitizing. (Cherry supplies a design package that includes a circuit schematic, final-layout sheet, test-program sheet and packaging-instruction sheet.) The firm then tools a metallization mask and completes processing and assembly. With orders of 50k or more, Cherry offers an optoelectronic transparent 8-lead DIP into which it will package a silicon photodiode plus a CS-2000 or CS-3000 design. The firm is also developing a combined I2 L/linear arrayโthe CS-4000.
If I2 L alone meets your technology needs, consider Dionics' three circuits: the SWAP-16, -24A and -24B, offering up to 400-gate complexity. Three development plans with varying levels of customer participation start at $2800 (least complexity, least Dionics participation) and range to a negotiable price that will certainly exceed $5000 (most complexity, most assistance).
Elapsed development time, exclusive of user tasks, is 6 to approximately 10 wks; production quantities can be ready 8 wks after prototype approval. Unit cost for a SWAP-24A in 10k quantities stands at $3.64, plus about $0.025 per gate or I/O circuit used.
One of the oldest companies in the semicustom-IC business, Exar started production in 1971. With a stable of seven linear circuits and four I2 L (one a combination I2 L/linear) configurations, this company has completed more than 300 semicustom designs covering a wide range of applications.
Exar has developed a 6-step design cycle involving three steps by the customer and three by the manufacturer. For a nominal added charge, it will undertake five of these stepsโyou need only provide a breadboard of your design. Assuming, however, that you execute just the three basic customer steps, development costs for a linear chip will range from $3000 to $5000 above design and layout expenses. I2 L-chip development costs start at $5000 and range to $10,000โdepending, as always, on complexity and the part employed. Linear development times usually range from 6 to 8 wks after pencil layout, while I2 L programs take 8 to 14 wks (this technology requires two additional masks).
Utilizing the fastest ECL family for its F200 gate array, Fairchild maintains F100K compatibility in the F200 to permit use of those standard-function parts. Designing with an F200 array, however, can be an expensive proposition: Development proceeds almost totally by computer.
Fairchild charges an entry fee of $20,000 to $25,000 and provides training (2 to 8 wks) in the use of software contained on Cybernet. Network design, employing macro-function cells, occurs by hand, but the next steps (test-vector generation and design verification) employ the TEGAS program on Cybernet. Macro interconnect and placement are partly manual and partly computer aided; design-rule checks are computer executed. Charges for computer time range from $5000 to $15,000, depending directly on your experience level.
Basic mask fabrication for an F200 array costs $10,000 to $15,000; Fairchild will also perform design and layout for an added $25,000 to $30,000. (Now you know why mainframe computers aren't cheap!)
The F200 is also available in an alternate low-power version, the F201, which consumes only 40% as much power. And now in development and planned for introduction in the first quarter of next year, Fairchild's 2000-gate F300 will feature eight times the complexity of the F200 and come in three power levels: 8, 4 and 2W. Propagation delays for this high-power part will drop to 400 psec; it will come in a leadless 150- to 180-pin package.
Also in the works at Fairchild is a part fabricated in I3 L (an I2 L technology developed by the firm) with 4000-gate complexity, whose target speed for gate delays stands at 6 nsec. Designated the 9480, it will replace entire boards of 74LS devices. To aid in the design of these complex units, Fairchild is working on software to accomplish autorouting, autoplacement, autotest and simulation.
CMOS packs 'em in
When it comes to technology, no firm can match Interdesign for sheer diversityโthe company offers designs executed in six different logic families. Not surprisingly, Interdesign has integrated more than 1000 designs, not including those produced by its parent company, Ferranti.
No matter which technology you choose, Interdesign charges $2800 for its services, which include taking a completed 200ร interconnect layout to completion of prototypes and final testing. Time for the company's part of the developmentโ4 to 6 wks.
As an aid, Interdesign provides a Monochip design kit ($59), consisting of a design handbook, kit parts for breadboarding and layout drawings. And one of the nicest features of the firm's policies is a redesign charge of only $900, at least on linear chipsโa provision that takes a lot of the pain out of making a design error.
Interdesign's digital gate arrays utilize CMOSโthe most widely used technology in the industry. Employed in both metal-gate and silicon-gate families, it seems to have an assured VLSI future. And because the technology combines low power, wide operating-voltage range, reliability, simplicity of design and densities that approach those of NMOS, it's no wonder that five other semicustom-IC manufacturers also employ it.
For the last 6 yrs, International Microcircuits has marketed an 11-member family of metal-gate CMOS, termed MasterMOS, with complexities of 50 to 550 gates. And in 1978, the firm introduced a silicon-gate CMOS line: the HS-MasterMOS family. In line with the drive toward greater density, product complexity in this latter family ranges from 200 to 2000 gates. The devices operate at 5V, and gate delays equal less than 5 nsec, allowing toggle rates to reach 30 MHz. The second quarter of this year will see this family expanded to 2000- to 5000-gate levels and providing 5V gate delays of less than 3 nsec.
Complete service from International Microcircuits, ranging from specification and logic-diagram stages to design of production-test hardware, takes almost all of the load off any customer who needs such treatment. The only step you need take is manual layout check; ultimate responsibility for layout correctness rests with you. A typical womb-to-tomb service package for the MasterMOS-550 chip runs about $16,000 and takes between 6 to 8 wks, exclusive of manual layout check.
Two other companies in the CMOS field, Master Logic and Microcircuits Technology, produce arrays with approximately 600-gate densities. Master Logic, in fact, designed the CMOS devices being produced by Interdesign under a nonexclusive license; the firm's ML100, 150 and 350 are identical with the MCA, B and D from Interdesign.
Master Logic also likes to get involved in the development cycle at an early stage and will perform prelayout engineering for $1500 to $4000. From layout to prototype, parts for the ML600 run to $20,000, and production hardware for some of the less dense circuits costs $1500 to $4000.
Design procedures at Microcircuits Technology essentially follow those in the rest of the industry. Charges for service on the company's high-density Masterchip 636 reach $12,500.
Library of macros
Anticipating the move to fully computerized design aids, Motorola has built its Macrocell Array from cells containing transistors and resisters not connected into gates. To configure these cells into SSI and MSI blocks, you choose among a library of macros that define functions ranging in complexity from a flip flop to a combination full adder and half adder. The computer stores the internal connection pattern for these macros and automatically generates the pattern for a chosen function; your job centers on macro placement and interconnection.
The Macrocell Array contains 106 cells; presently, you can choose among 85 different macros. The ECL product is MECL 10K compatible. Using a hookup to Motorola's Western Area Computer Center, you do most of the development work, while Motorola does the tooling, production and testing. The charge for services is $40,000, exclusive of computer time and terminal rental.
Designers employing any of Signetics' arrays (I2 L and ISL) will also find themselves hooked to a computer, though not to the exclusion of manual layout and checkout. Actually, the company offers four different customer-interface plans, depending on your resources and equipment.
Services charges for a Signetics I2 L design run to $30,000, including 150 min of computer time to run TEGAS test-vector generation and simulation. Signetics' primary efforts, however, lie in ISL arrays. A variant of I2 L, ISL combines the low power and packing density of I2 L with the speed of Schottky TTLโobviously making it another VLSI-technology candidate. A 1200-gate array is now in production, and a 2000-gate chip is in development.
The more the merrier
The resurgence of interest in uncommitted logic is drawing new companies into both the semicustom and fuse-programmable fields. For example, look for an announcement from AMI in about the third quarter of this year regarding a line of silicon-gate CMOS semicustom arrays. And expect some words from Harris Semiconductor on an FPLA.
Also note that National Semiconductor is covering all bets: It announced a marketing agreement with Motorola concerning Marcocell Array-derived parts last November and has recently announced its intention of producing some of the PAL device types. Pricing on those PAL products selected will start at about $50 but should drop substantially when National goes into full production.
| A brief history of uncommitted IC logic
The origin of semicustom devices is the subject of some dispute and several claims. As near as can be determined, the first available gate arrays came from Fairchild in 1967. This Micromatrix family began with a 32-gate DTL array with 20-nsec delays, fabricated on a die measuring 80ร110 mils. The next two devices were introduced in the following year, but by then size and complexity had risen, and the technology was TTL. The largest product covered a die measuring 145ร145 mils and had 144 gates and internal delays of 18 nsec. That same year (1968), three other companies announced TTL arrays. Sylvania produced the SL80, which had 30 cells, each containing four 4-input gates; customization required up to three layers of metal. Motorola introduced 25- and 80-gate arrays with propagation delays of 5 nsec and dissipation of 7.5 mW/gate. And Texas Instruments came out with its Master Slice, having several cells (each containing 16 gates) that could be connected (by means of two metal masks and a via mask) into logic functions. In 1971, Raytheon began marketing TTL gate arrays and by 1973 had produced the RA-116 Schottky TTL array, which it still sells. Also around this time, more of the big manufacturers (such as RCA and Hughes) moved into the business, while most of the pioneers dropped out. In this same period, three new companies specializing in custom arraysโInterdesign, Exar and International Microcircuitsโhelped take up the slack. Additionally, in 1972 the British-based Ferranti Electronics Ltd introduced its ULA (uncommitted logic array) line and has been a major force in semicustom logic ever since, especially following its acquisition of one of the other market leadersโInterdesign. With the renewed interest in semicustom ICs evident since 1976, Fairchild, Texas Instruments and Motorola have returned to the marketโFairchild and Motorola in ECL arrays and Texas Instruments in I2 L and STL (Schottky transistor logic), a technology similar to ISL (integrated Schottky logic) but said to be faster. Interest has not been confined to the US, either; Europe has at least four manufacturers (Ferranti, Philips, Plessey and Siemens), while in Japan, Fujitsu, Hitachi and NEC are prominent. In the other main area of uncommitted logic, the fuse-programmable FPLA got its start at Signetics in 1975 as an outgrowth of the chrome fuse processing employed in bipolar ROMs. The same period saw the introduction of the ยตP, and debate raged over which would supplant the other. The ยตP has taken center stage until now, but the newer versions of fuse-programmable logic are gaining a piece of the action from both ยตPs and semicustom gate arrays. Current manufacturers of FPLAs and related devices include Signetics, Intersil, Monolithic Memories, Fairchild, National Semiconductor and Raytheon Semiconductor. |
| A review of field-programmable logic
By Napoleone Cavlan, Signetics Corp With the large-scale integration of memory, processor, control and I/O functions, a vast array of devices is now available for combining, in a few chips, system architectures that once required dozens or even hundreds of discrete-logic circuits. Yet despite a wide choice of standard functions, it's still virtually impossible to complete a design without employing some discrete logic to support the main framework. Spurred by the trend toward distributed processing, mask-programmable bipolar and MOS gate arrays have emerged in densities up to about 5000 gates/chip. With nearly total design flexibility, these devices are tailorable into low-cost, high-performance custom functions for data computation, data movement and translation in distributed-intelligence networks. But the use of this technology entails a substantial investment in time and resources; you must collaborate with a semiconductor house in setting up compatible development systems to generate system logic diagrams, functional-test sequences, logic conversions to gate-array patterns, software and/or hardware simulations, gate-interconnect diagrams, mask development, prototype fabrication and evaluation. The design cycle can take 6 to 12 months and can be further delayed by the inevitable iterations arising from intervening design modifications. And there is no recourse for errors discovered after commitment to production. Thus, gate arrays are mainly suited to large, well-defined systems slated for high-volume production. Whether you employ standard functional logic blocks or custom gate arrays, today's design trends yield recurring patterns of large functional islands, coupled by logic bridges. Because of complexity, performance or uniqueness requirements, designing these bridges usually involves nontrivial random-logic configurations relying upon clusters of discrete MSI and SSI arrays with fixed functions and configurations. Recently, a new degree of flexibility has appeared in this area, in the form of a field-programmable logic family (FPLF) consisting of fast user-programmable logic devices with memory. These devices can streamline logic design by integrating the functional equivalent of hundreds of TTL gates in a few compact and flexible elements. Signetics' FPLF consists of single-level, 2-level and registered logic elements of increasing logic power and complexity. It currently includes eight devices, each housed in a 28-pin package. A 20-pin chip set, based on a similar architecture, is in the works to cover lower-end applications requiring less I/O capacity. The devices in the current Signetics FPLF contain such logic elements as AND gates, OR gates S/R flip flops, true/complement buffers and XOR gates. Programming proceeds via Ni-Cr fusible links that couple the inputs and outputs of on-chip AND, OR and XOR gate arrays. These links form arrays of cross-point connections which are initially intact; you obtain the desired logic function by selectively fusing links open as required, using readily available programming equipment. At each level of complexity, all elements in the family incorporate features that maximize user flexibility in tailoring each device to the requirements of a specific application. Such applications include fault monitors, memory-protect logic, priority encoders, bus protocols, sequence detectors, bit/byte synchronizers and peripheral controllers. Because all devices can be programmed and modified in the field, you can plan a flexible logic system that's updateable to meet new customer requirements or specifications or to recover from design errors discovered after delivery to the field. The approach also provides a competitive edge, not only by furnishing more functions along with speed and cost advantages, but by speeding your development cycle. Napoleone Cavlan is product marketing manager at the Sunnyvale, CA manufacturer. |
| The semicustom concept
By Derek Bray, Interdesign Inc Semicustom ICs are designed and fabricated utilizing โstandardโ wafers consisting of predesigned component arrays. These arrays can be interconnected in many different ways by means of one or more steps; the most common interconnection procedure utilizes single-layer metal patterning of the wafers, although customization of contact locations is also possible. The component arrays are usually designed to serve particular applications. Processes currently employed include:
The advantages of the semicustom concept are significant when compared with other approaches. They include:
The approach's viability has been demonstrated by wide industry acceptance in automotive, telecommunications, industrial, military, consumer, medical and computer applications. Present applications cover the full range of analog, digital and combination analog/digital circuits. Production volumes can range from 100 to one million devices per year. Derek Bray is vice president for engineering at the Sunnyvale, CA firm. |
| A PAL review
By John Birkner, Monolithic Memories Inc PAL stands for โprogrammable array logicโ; there are currently 15 devices in the PAL family manufactured by Monolithic Memories and second-sourced by National Semiconductor. The devices range in complexity from combinatorial to sequential and arithmetic; they replace conventional 7400 Series TTL gates, MUXs, decoders, encoders, flip flops, shift registers and counters and achieve a fourfold to twelvefold package-count reduction. Features include:
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