Opensource DDR3 Controller
-
Updated
Jun 14, 2025 - Verilog
#
ddr3
Here are 21 public repositories matching this topic...
A DDR3(L) PHY and controller, written in Verilog, for Xilinx 7-Series FPGAs
-
Updated
Dec 1, 2022 - Verilog
mirror of https://git.elphel.com/Elphel/eddr3
-
Updated
Oct 16, 2017 - Verilog
A RISC-V SBC based around the LambdaConcept USB2Sniffer FPGA board.
-
Updated
May 10, 2020 - Verilog
Demo board for the i.MX6ULL Single-Core Processor with Arm Cortex-A7 Core
-
Updated
Nov 27, 2024
A curated list of awesome Rowhammer papers, tools, and info resources. 👉 Content coming soon, stay tuned!
academic awesome-list dram attacks hardware-security ddr3 rowhammer defenses ddr4 ddr5 hardware-attacks
-
Updated
Jun 17, 2022
An attempt at making a 2-way superscalar out-of-order riscv processor for an Arty s25 fpga.
processor-architecture fpga processor out-of-order superscalar risc-v processor-simulator ddr3 processor-design axi4 superscalar-cpu
-
Updated
Oct 7, 2024 - SystemVerilog
Improve this page
Add a description, image, and links to the ddr3 topic page so that developers can more easily learn about it.
Add this topic to your repo
To associate your repository with the ddr3 topic, visit your repo's landing page and select "manage topics."