vitis-hls

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The source codes used in the blog post available at: https://rayanfam.com/topics/hardware-design-stack/

asic fpga vhdl chisel chisel3 verilog vivado gtkwave modelsim netlist verilator vivado-hls asic-design vitis openram openlane vitis-hls

Deep Learning Aided Radar Signal Processing on Zynq SoCs for Doppler Estimation with hardware (Zynq SoC IPs)

music zynq driver jupyter-notebook dnn neural-networks vivado root-music esprit vivado-hls pynq-z2 vitis zcu111 vitis-hls

2025. Fully maintained, working implementation on a PYNQ Z1/Z2 board (Latest release: Vivado 2024.2 & Vitis 2024.2)

fpga vivado high-frequency-trading vitis vitis-hls

fpga svm vhdl speech-recognition vitis-hls

FPGA accelerator for real-time hand gesture recognition using QKeras and HLS4ML on Zynq UltraScale+ (PYNQ)

embedded fpga zynq vivado pynq gesture-recognition tinyml hls4ml vitis-hls qkeras

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